Hybrid Memory Device for Superconducting Computing

A team of NIST scientists has devised and demonstrated a novel nanoscale memory technology for superconducting computing that could hasten the advent of an urgently awaited, low-energy alternative to power-hungry conventional data centers and supercomputers.

In recent years, the stupendous and growing data demands of cloud computing, expanded Internet use, mobile device support, and other applications have prompted the creation of large, centralized computing facilities at hundreds of thousands of sites around the world.

Such facilities typically run 24 hours a day and employ arrays of semiconductor-based servers which require substantial amounts of electricity and generate correspondingly substantial amounts of heat – which in turn requires yet more energy to remove.*

Even if the power needs for all U.S. data centers – estimated to grow from 72 terawatt hours (TWh) to 200 TWh by 2020, roughly 5% of all electricity consumed in the nation – can be met, the inherent constraints of semiconductor electronics will still set scaling and clock-rate limits on future processing capacity at a time when digital information volume is increasing exponentially.

One promising replacement technology is superconducting (SC) computing, which offers the prospect of moving information without loss over zero-resistance channels. Instead of using semiconductor transistors to switch electronic signals, SC systems employ tiny components called Josephson junctions** (JJs). JJs operate near absolute zero (in the range of 4 K to 10 K), dissipate minuscule amounts of energy (less than 10^-19 joule per operation), and can be switched between states at hundreds of billions of times a second (frequencies of gigahertz), compared to a few gigahertz for semiconductor computers.

To date, however, many key technologies required for a working SC computer – such as logic circuits, component interconnects, and most notably cryogenic memory – have not been developed. But the Intelligence Advanced Research Projects Activity (IARPA) has determined that, thanks to recent research progress, the “foundations for a major breakthrough” are now in place, and has launched a multi-year program to investigate the practical viability of SC computing.

NIST scientists have been engaged to develop the necessary metrology and evaluation methods for the IARPA program; but long before the program began they had been focusing on one of the most stubborn obstacles to SC computing: the lack of a memory system that can work at the cryogenic temperature and blazing speed of the JJ switches while also requiring minimal operating energy.

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