The number of transistors in a given space could be increased considerably, along with the performance capacity of microprocessors and memory units.
The team from Laboratoire d’Analyse et d’Architecture des Systèmes (LAAS-CNRS, Toulouse) and Institut d’Électronique, de Microélectronique et de Nanotechnologie (IEMN) developed the 3D architecture consisting of a vertical nanowire array whose conductivity is controlled by a gate measuring 14nm in length. Published in Nanoscale, their findings are said to open the way toward alternatives to the planar structures used in microprocessors and memory units as the use of 3D transistors could significantly increase the power of microelectronic devices.
A team of researchers at the LAAS and IEMN has now built a 3D nanometric transistor that consists of a tight vertical nanowire array of about 200nm in length linking two conductive surfaces. A chromium gate completely surrounds each nanowire and controls the flow of current, resulting in optimum transistor control for a system of this size. The gate is 14nm in length, compared with 28nm for the transistors in today’s chips, but its capacity to control the current in the transistor’s channel meets the requirements of contemporary microelectronics.
This architecture could lead to the development of microprocessors in which the transistors are stacked together. The number of transistors in a given space could be increased considerably, along with the performance capacity of microprocessors and memory units. Another advantage of these components is that they are relatively simple to manufacture and do not require high-resolution lithography. In addition, it is claimed these 3D transistors could be easily integrated into the conventional microelectronic devices used by the industry today.
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